1. Field of the Invention
The invention relates generally to a method of forming a metal interconnection layer in a semiconductor device. More particularly, the invention relates to a method of forming a metal interconnection layer in a semiconductor device by which a metal seed layer is processed by a laser and a metal film is formed using an electroplating method.
2. Description of the Prior Art
A plating method includes an electroless plating method and an electroplating method. The electroless plating method has advantages that it can obtain a good gap filling characteristic and a high-speed growth even in a line structure having a high aspect ratio. However, this method has disadvantages that tolerance against the electro migration (hereinafter call EM) is low since the grain size is small and the process is also difficult to control due to complicated chemical reaction. On the other had, the electroplating method had advantages that the growth speed is faster, chemical reaction is relatively simple, it is easy to handle, the grain size is large, a good film quality can be obtained and tolerance against EM is thus good. However, the electroplating method has an disadvantage that it necessarily requires a seed layer.
The electroplating method is one by which a membrane of other metal is formed in metal or nonmetal devices using an electric energy. Electrolysis means that physical or chemical change is caused by the electric energy from the outside. Upon electrolysis, the electrolytic cell includes two electrodes of anode and cathode, and an electrolyte existing between the two electrodes. In other words, electroplating of metal is performed with the surface of the conductive material contained in a solution where plated metal is melt. The surface of the conductive material is electrically connected to an external power supply. Current thus flows into the solution through the surface of the conductive material. If so, metal ions react with electrons to form a metal. Deposition is performed based on this principle.
However, in the process of forming the cupper line using the above electroplating method, it is necessarily required that the seed layer be uniformly deposited. A method of depositing the seed layer, which has been recently used, employs a physical vapor deposition method. In the method of forming the copper line using this method, a copper anti-diffusion barrier layer and a copper seed layer are formed by means of the physical vapor deposition method. A copper film is then formed on them by means of the electroplating method, thus burying a via or a trench. The method of forming the copper line is finished by means of a chemical mechanical polishing process. However, the process for forming the copper seed layer using the physical vapor deposition method has problems that an overhang may happen in the via or the trench having a high aspect ratio due to poor layer coverage, and void may be formed within the via or trench in a subsequent copper electroplating process due to discontinuous points of deposition. In order to solve these problems, a research on formation of the copper seed layer using a chemical vapor deposition method has been made. However, this chemical vapor deposition method has disadvantages of poor adhesive force, instability, expensive cost, and the like.
The present invention is contrived to solve the above problems and an object of the present invention is to provide a method of forming a metal interconnection layer in a semiconductor device by which a dual damascene pattern, a via hole or a trench having a high aspect ratio can be filled with a metal film consecutively without void by means of an electroplating method.
In order to accomplish the above object, the method of forming the metal interconnection layer in the semiconductor device according to the present invention, is characterized in that it comprises the steps of forming a lower conductive layer on a semiconductor substrate, forming an interlayer insulating film on the semiconductor substrate on which the lower conductive layer is formed, selectively etching the interlayer insulating film to form an opening of a given shape through which the lower conductive layer is exposed, forming a metal seed layer along the step on the result in which the opening of the given shape is formed, reflowing the metal seed layer by means of a laser process to form the metal seed layer of an uniform thickness, performing a hydrogen reduction annealing process for the metal seed layer, and forming a metal film on the metal seed layer by means of an electroplating method.
The laser process may be performed using nitrogen or helium as light source of a laser.
It is preferred that the laser process includes illuminating the laser beam at the energy intensity of 1 through 5 mJ/cm2 and application voltage of 1 through 20 KV.
The laser process may include illuminating the laser beam by moving the semiconductor substrate to scan with the light source of the laser being fixed, or by moving the light source of the laser to scan the semiconductor substrate with the semiconductor substrate being fixed.
The laser process may include illuminating the laser beam by reflecting the laser emitted from a laser discharge device using a reflecting mirror and making the focus of the laser beam using a focus control means in order to control the energy intensity.
The laser process may include illuminating the laser beam by positing a slit between a focus control device and the semiconductor substrate and then controlling the intensity of the laser beam emitted from the focus control device.
The metal seed layer may be formed of copper (Cu), nickel (Ni), molybdenum (Mo), platinum (Pt), titanium (Ti) or aluminum (Al).
It is preferred that the metal seed layer is formed in thickness of 50 through 2500 xc3x85.
The hydrogen reduction annealing process is performed using a hydrogen gas, or a hydrogen-mixed gas containing argon (Ar) or nitrogen (N2) of a given concentration at room temperature through 350xc2x0 C. for 1 minute through 3 hours, in order to make rough the grain size of the metal seed layer and remove a native oxide film formed on the surface of the metal seed layer.
The method may further include the step of forming a diffusion barrier layer on the semiconductor substrate in which the opening is formed before the metal seed layer is formed.
The method further comprises the steps of after the metal film is formed using the electroplating method, performing a hydrogen reduction annealing process for the metal film, and performing a chemical mechanical polishing process for the semiconductor substrate in which the metal film is formed.
The metal film is a copper (Cu) film.
The opening of the given shape is a dual damascene pattern, a via hole or a trench.